ST7LITE05 datasheet(32/122 Pages) STMICROELECTRONICS

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.5.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read /Write

Reset Value: 0000 0x00 (0xh)

Bit 7:4 = Reserved, must be kept cleared.

Bit 3 = LOCKED

PLL Locked Flag

This bit is set and cleared by hardware. It is set au-

tomatically when the PLL reaches its operating fre-

quency.

0: PLL not locked

1: PLL locked

Bit 2 = LVDRF

LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware (LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description in Section 11.1 for more

details. When the LVD is disabled by OPTION

BYTE, the LVDRF bit value is undefined.

Bit 1 = AVDF

Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE bit is set, an interrupt request is gen-

erated when the AVDF bit changes value. Refer to

Figure 19 for additional details

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 = AVDIE

Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this case, a watchdog reset can be detected by

software while an external reset can not.

Table 6. System Integrity Register Map and Reset Values

000

LOCK

LVDRF AVDF AVDIE

Address

(Hex.)

Label

7654

3210

003Ah

SICSR

Reset Value

0000

LOCKED

LVDRF

AVDF

AVDIE

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