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ST7LITE05 数据表(PDF) 34 Page - STMicroelectronics |
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ST7LITE05 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 122 page  ST7LITE0, ST7SUPERLITE 34/122 INTERRUPTS (Cont’d) Figure 20. Interrupt Processing Flowchart Table 7. Interrupt Mapping I BIT SET? Y N IRET? Y N FROM RESET LOAD PC FROM INTERRUPT VECTOR STACK PC, X, A, CC SET I BIT FETCH NEXT INSTRUCTION EXECUTE INSTRUCTION THIS CLEARS I BIT BY DEFAULT RESTORE PC, X, A, CC FROM STACK INTERRUPT Y N PENDING? N° Source Block Description Register Label Priority Order Exit from HALT Address Vector RESET Reset N/A Highest Priority Lowest Priority yes FFFEh-FFFFh TRAP Software Interrupt no FFFCh-FFFDh 0 Not used FFFAh-FFFBh 1 ei0 External Interrupt 0 yes FFF8h-FFF9h 2 ei1 External Interrupt 1 FFF6h-FFF7h 3 ei2 External Interrupt 2 FFF4h-FFF5h 4 ei3 External Interrupt 3 FFF2h-FFF3h 5 Not used FFF0h-FFF1h 6 Not used FFEEh-FFEFh 7 SI AVD interrupt SICSR yes FFECh-FFEDh 8 AT TIMER AT TIMER Output Compare Interrupt PWM0CSR no FFEAh-FFEBh 9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h 10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h 11 LITE TIMER RTC Interrupt LTCSR yes FFE4h-FFE5h 12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h 13 Not used FFE0h-FFE1h 1 |
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