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ST7LITE05 数据表(PDF) 54 Page - STMicroelectronics |
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ST7LITE05 数据表(HTML) 54 Page - STMicroelectronics |
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54 / 122 page ![]() ST7LITE0, ST7SUPERLITE 54/122 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATC- SR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:5 = Reserved, must be kept cleared. Bit 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. The change be- comes effective after an overflow. Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred Caution: When set, the OVF bit stays high for 1 fCOUNTER cycle, (up to 1ms depending on the clock selec- tion). Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled 1: OVF interrupt enabled Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and clear by hardware after a reset. It allows to mask the inter- rupt generation when CMPF bit is set. 0: CMPF interrupt disabled 1: CMPF interrupt enabled COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (00h) COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incre- mented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations, LSB first. When a counter over- flow occurs, the counter restarts from the value specified in the ATR register. 70 0 0 0 CK1 CK0 OVF OVFIE CMPIE Counter Clock Selection CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 0 1 fCPU 10 Reserved 1 1 15 8 0000 CN11 CN10 CN9 CN8 70 CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0 1 |
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