1/15

STA120

December 2002

s

MONOLITHIC CMOS RECEIVER

s

3.3V SUPPLY VOLTAGE

s

LOW-JITTER, ON-CHIP CLOCK RECOVERY

256xFs OUTPUT CLOCK PROVIDED

s

SUPPORTS: AES/EBU, IEC 958, S/PDIF, &

EIAJ CP-340/1201 PROFESSIONAL AND

CONSUMER FORMATS

s

EXTENSIVE ERROR REPORTING REPEAT

LAST SAMPLE ON ERROR OPTION

DESCRIPTION

The STA120 is a monolithic CMOS device that re-

ceives and decodes audio data according to the

AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201

interface standards.

The STA120 recovers the clock and synchroniza-

tion signals and de-multiplexes the audio and dig-

ital data. Differential or single ended inputs can be

decoded.

The STA120 de-multiplexes the channel, user and

validity data directly to serial output pins with ded-

icated output pins for the most important channel

status bits.

SO28

ORDERING NUMBER: STA120D

DIGITAL AUDIO INTERFACE RECEIVER

BLOCK DIAGRAM

AUDIO

SERIAL PORT

REGISTERS

DE MUX

CLOCK & DATA

RECOVERY

C0/E0

M2

M0

AGND

FILT

SDATA

SCK

FSYNC

C

U

VREF

ERF

CBL

RXP

9

25

15

26

12

11

23

18

6

1

14

28

D97AU613A

M1

24

VA+

MCK

8

7

DGND

VD+

19

21

20

22

RS422

Receiver

RXN

10

MUX

13

CS12/FCK

16

SEL

MUX

Ca/E1

5

Cb/E2

4

Cc/F0

3

Cd/F1

2

Ce/F2

27

M3

17