STA120

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frequency detectors pull the VCO frequency within

the lock range of the PLL. When no digital audio

data is present, the VCO frequency is pulled to its

minimum value.

Figure 2. Jitter Attenuator Characteristics.

As a master, SCK is always MCK divided by four,

producing a frequency of 64 x FS. In the STA120,

FSYNC is always generated from the incoming

data stream. When FSYNC is generated from the

data its edges are extracted at times when in-

tersymbol interference is at a minimum. This pro-

vides a sample frequency clock that is as

spectrally pure as the digital audio source clock for

moderate length transmission lines.

STA120 DESCRIPTION

The STA120 does not need a microprocessor to

handle the non-audio data (although a micro may

be used with the C and U serial ports). Instead,

dedicated pins are available for the most important

channel status bits. The STA120 is a monolithic

CMOS circuits that receives and decodes digital

audio data which was encoded according to the

digital audio interface standards. It contains a

clock and data recovery utilizing an on-chip phase-

locked loop. The output data is output through a

configurable serial port that supports 14 formats.

The channel status and user data have their own

serial pins and the validity flag is OR'ed with the

ERF flag to provide a single pin, VERF, indicating

that the audio output may not be valid. This pin

may be used by interpolation filters that provide er-

ror correction.

Audio Serial Port

The audio serial port is used primarily to output au-

dio data and consists of three pins: SCK, FSYNC

and SDATA. These pins are configured via four

control pins: M0, M1,M2,and M3.M3 selects be-

tween eight normal serial formats (M3 = 0), and six

special formats (M3 = 1).

Normal Modes (M3 = 0)

When M3 is low, the normal serial port formats

shown in Figure 3 are selected using M2, M1 and

M0. These formats are also listed in Table 1

wherein the first word part the format number (Out-

In) indicates whether FSYNC and SCK are outputs

from the STA120 or are inputs.

The next word (L/R-WSYNC) indicates whether

FSYNC indicates the particular channel or just de-

lineates each word. If an error occurs (ERF=1)

while using one of these formats, the previous val-

id audio data for that channel will be output.

If the STA120 is not locked, the last sample is re-

peated at the output. In some modes FSYNC and

SCK are outputs and in others they are inputs. In

Table 3, LSBJ is short for LSB justified where the

LSB is justified to the end of the audio frame and

the MSB varies with word length. As outputs the

STA120 generates 32 SCK periods per audio

sample (64 per stereo sample) and, as inputs, 32

SCK periods must be provided per audio sample.

When FSYNC and SCK are inputs, one stereo

sample is double buffered. For those modes which

output 24 bits of audio data, the auxiliary bits will

be included. If the auxiliary bits are not used for

audio data, they must be masked off.

1

10

100

1000

(KHz)

100

75

50

25

(dB)

D97AU612