STA120

4/15

Note 1: FS is defined as the incoming audio sample frequency per channel.

Note 2: The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio

samples). Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode 32 SCK periods must

be provided in most serial port formats.

16

SEL

Select.Control pin that selects either channel status information (SEL = 1) or error and frequency

information (SEL = 0) to be displayed on six (C0, Ca Cb, Cc, Cd, Ce) pins.

27

Ce

Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is

high. Channel status information is displayed for the channel selected by CS12. C0, which is

channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further

controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.

F2

Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL

low. A proper clock on FCK must be input for at least two thirds of a channel status block for

these pins to be valid. They are updated three times per block, starting at the block boundary.

28

VERF

Validity + Error Flag. A logical OR'ing of the validity bit from the received data and the error flag.

May be used by interpolation filters to interpolate through errors.

Receiver Interface

9

RXP

Line Receiver. (RS422 compatible)

10

RXN

Line Receiver. (RS422 compatible)

Phase Locked Loop

19

MCK

Master Clock.Low Jitter clock output of 256 times the received sample frequency.

20

FILT

Filter.An external 330 Ohm resistor and 0.47

µF capacitor in parallel with a 15nF capacitor is

required from FILT pin to analog ground.

25

ERF

Error Flag,Signals that an error has occurred while receiving the audio sample currently being

read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation

during the current sample, or an out of lock PLL receiver.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Power supply voltage Range

3.0

3.3

3.6

V

High-Level Input Voltage

2.0

V

Low-Level Input Voltage

+0.8

V

High-Level Output Voltage

V

Low-Level Output Voltage

0.4

V

Input Leakage Current

1.0

10

µA

Input Sample Frequency

(Note 1)

25

96

kHz

MCK

Master Clock frequency

(Note 1)

6.4

256xFS

25

MHz

MCK Clock Jitter

300

ps RMS

MCK Duty Cycle

(high time/cycle time)

50

%

0.1

1

mA

Dynamic Idd

6

15

mA

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SCK Frequency

(Note 2)

OWRx32

Hz

PINS DESCRIPTION (continued)

N.

Name

Description