STLC1512

16/26

4.6 Digital Interface Logic Level

4.7 ESD and Latch Up

5.0 APPLICATION DIAGRAM

To reduce the power consumption of the power amplifier, the two output power transistors of the power amplifier

are powered by a switching power supply at the center tap of the transformer. (See Figure 7.) The switching is

controlled by the digital chip (STLC1510) that senses the future signal level.

The stability and offset of the power amplifier are optimized with the feedback scheme and the component val-

ues shown in this application diagram. As such, the application of the STLC1512 has to follow the topology and

component values in the diagram to avoid stability and offset problems.

Table 13. Definition of Logic Levels for Digital Control Input Pins

SYMBOL

DESCRIPTION

MIN

NOM

MAX

UNITS

COMMENTS

VIL

Input low voltage

0.8

V

Signal from STLC1510

VIH

Input high voltage

2.0

V

Signal from STLC1510

Table 14. ESD and Latch up

Parameter

Conditions

Min

Obj

Max

Unit

<1>Test assumes standard Human body ESD model. Industry standard requirement is 1kV.

12

kV

Latchup current

100

200

mA