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Appendix E - Board Issues for Heat Dissipation

this happens.

There are various combinations of maximum ambient temperature and board issues that can contribute to the

junction temperature of the devices on the chip. Different layout techniques can be used to enhance the thermal

coefficient of the package. The following conditions must be true to ensure reliable operation of the line driver.

(EQ E.1)

The thermal coefficient is determined by the board layout characteristics and the rate that air is being forced

across the board. The board layout is defined in 2 ways. One is a 2 layer board with signal layers on the top and

bottom. The signal layer has a heat spreading copper plane that spreads from the corner pins of the chip. There

are also thermal vias directly under the chip. The second layout is an 8 layer board with signal layers on the top

an bottom, 4 copper lattice planes (80% 1 ounce copper) and 2 copper ground planes (solid 1 ounce copper).

This layout also has a heat spreading copper plane on the signal layer and thermal vias under the die and in the

copper plane.

The thermal coefficients for these two different boards are given in Table 15. These coefficients are modified

based on the amount of air flow over the board..

Table 15. Thermal Coefficients for Different Board Conditions

Board Type

2 Layer

87.2

75.6

63.6

59.4

8 Layer

54.7

50.6

48.0

46.1

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