STLC1512

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32

TXVCC2

VCC

+5.0V supply for power amp output stage

33

TXVCC3

VCC

+5.0V supply for Tx path circuitry and bias blocks

34

AMPOUT

AO

Undedicated opamp output

35

AMPIN

AI

Undedicated opamp negative input

36

AMPIP

AI

Undedicated opamp positive input

37

DCFBON

AO

Power amp DC feedback amplifier negative output

38

DCFBOP

AO

Power amp DC feedback amplifier positive output

39

TXANG

AO

2.5V Tx buffered reference

40

FPP

AO

Fast path positive output

41

FPN

AO

Fast path negative output

42

PAIP

AI

Tx Power amplifier positive input

43

PAIN

AI

Tx Power amplifier negative input

44

RBIAS

AO

Reference resistor generating bias current

45

REF2P5

AI

Externally supplied 2.5V reference

46

NC

Not connected

47

LPFOUT

AO

LPF (low pass filter) Op Amp output

48

LPFIN

AI

LPF (low pass filter) Op Amp negative input

<1>The values of the components that are connected to the pins are shown in Figure 11.

<2>If the undedicated opamp is used in the transmit path, AMPPD can be connected to TXPD on the board. If the undedicated opamp

is used in the receive path, AMPPD can be connected to RXPD on the board. This opamp is powered off of TXVCC3.

Table 1. Pin Description

3.0 FUNCTIONAL DESCRIPTION

The STLC1512 consists of the following functional

blocks:

s

Transmit Signal Path

s

Receive Signal Path

s

Thermal Protection

The transmit signal that comes from the AFE is fil-

tered before it reaches the line driver. STLC1512

contains an opamp that can be utilized as part of this

filter. The AMPPD pin allows this op amp to be pow-

ered down independently. The line driver consists of

a preamp followed by a current drive power stage.

The preamplifier provides large open loop gain while

the power stage provides open collector current drive

to allow for single supply switching. The center tap of

the primary side of the transformer is connected to a

supply that can be switched between 5.0V and a low-

er supply to realize power savings on a DMT signal.

The reference design sets this supply at 3.3V. The

line driver can be powered down by a low at the

TXPD pin.

The receive path consists of a Programmable Gain

Amplifier (PGA) and an active low pass filter. The

PGA is programmable in four steps. The active low

pass filter is composed of an on chip op amp and ex-

ternal passive components. The receive signal pass-

es through the PGA, is low pass filtered and then

driven off chip to the AFE chip. Both the PGA and the

opamp can be powered down by RXPD signal.

A thermal protection circuit has also been implement-

ed on the chip to prevent the chip from overheating

under fault conditions.

4.0 SPECIFICATIONS

4.1 Chip Specifications

The cross-talk specifications are based on the as-

sumption that cross-talk should not degrade the

SNDR of the receive signal. If there is receive cross-

talk into the transmit path, this signal will come back

through the hybrid balance and cause noise in the re-

ceive path. If the signal is undistorted it will cause a

small gain and phase error which will not affect per-

formance. If it is distorted it will cause an increased