STLC5464 datasheet(79/83 Pages) STMICROELECTRONICS

79 / 83 page

Receiver

: Tx = 0, Receiver

A4/0

: Rx HDLC Channel 0 to 31

ERF

: Error detected on Received Frame

An error such as CRC not correct, Abort, Overflow has been detected.

EOQ

: End of Queue

The receive DMA Controller has encountered the current receive Descriptor with EOQ at ”1”.

DMA Controller is waiting ”Continue” from microprocessor.

HALT

: The Receive DMA Controller has received HALT or ABORT (on the outside of frame) from the

microprocessor; it is waiting ”Continue” from the microprocessor.

: Buffer Filled

If IBC bit of Receiver Descriptor is at ‘1’, the Receive DMA Controller puts BF at”1” when it has

filled the current buffer with data from the received frame.

CFR

: Correctly Frame Received

A receive frame is ended with a correct CRC. The end of the frame is located in the last descriptor

if several Descriptors.

IX.5 - Receive Command / Indicate Interrupt

IX.5.1 - Receive Command / Indicate Interrupt when TSV = 0

Time Stamping not validated (bit of GCR Register)

bit15

bit8

bit7

bit 0

This word is located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this

interrupt queue located in the external memory.

: New Status.

Before writing the features of event in the external memory the Interrupt Controller reads the

NS bit :

if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has

been received.

if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).

When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new

status. This location becomes free for the Interrupt Controller.

: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.

G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.

A2/0

: COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1

C6/1

: New Primitive received twice consecutively

IX - EXTERNAL REGISTERS (continued)

STLC5464

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