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STLC5464 数据表(PDF) 22 Page - STMicroelectronics |
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STLC5464 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 83 page ![]() TIME S LOT AS S IGNE R 32 Rx HDLC 32 ADDRE S S RE COGNITION 32 Rx FIFO ’s 32 Rx DMAC 32 Rx DMAC 32 Tx FIFO ’s 32 Tx HDLC 32 CS MA-CR DIN 8 Dire ct HDLC Input F rom Output 7 of the Matrix To Input 7 of the Matrix From Output 6 of the Matrix DO UT 6 Direct HDLC O utput Conte ntion Bus Echo µP INTERFACE RAM INTER FACE Figure 8 : HDLC and DMA Controller Block Diagram III - FUNCTIONAL DESCRIPTION (continued) STLC5464 22/83 |
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