STLC5464 datasheet(39/83 Pages) STMICROELECTRONICS

部件名	STLC5464

功能描述	MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

PDF	83 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

39 / 83 page

V - CLOCK TIMING (continued)

V.2 - TDM Synchronization

Bit 0, Time Slot 0

DCLK de live re d by

the Multi-HDLC

FS CG d e livere d by

the Multi-HDLC

DOUT0/7, CB

DIN0/8

The four Multiplex Configura tion Re giste rs a re a t z e ro (no d e lay be twe e n FS a nd Multiplexe s).

CLOCK A (o r B)

Bit 7, Time S lot 31

ECHO

Figure 28 : Synchronization Signals received by the

Multi-HDLC

Symbol

Parameter

Min.

Typ.

Max.

Unit

Clock Period if 4096kHz

Clock Period if 2048kHz

Id CLOCKA or B

244

488

Id CLOCKA or B

Delay between CLOCK A or B and DCLK (30pF)

Set-up Time FS/DCLK

t1-20

Hold Time FS/DCLK

Duration FS

244

125000-244

DCLK to Data 50pF

DCLK to Data 100pF

100

Set-up Time Data/DCLK

Hold Time Data/DCLK

Set-up Echo/DCLK (rising edge)

155

Hold Time Echo/DCLK (rising edge)

205

STLC5464

39/83

STLC5464 数据表(PDF) 39 Page - STMicroelectronics

STLC5464 数据表(HTML) 39 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载