STLC5465B datasheet(87/101 Pages) STMICROELECTRONICS

87 / 101 page

A, E, S1 to S4: 6 bit word transmitted. Case of D=1.

PT0/1 : Status bits

Primitive Status

Primitive (or 6 bit word) has not been transmitted yet.

Primitive (or 6 bit word) has been transmitted once.

Primitive (or 6 bit word) has been transmitted twice.

Primitive (or 6 bit word) has been transmitted three times or more.

VIII.23 - Transmit Monitor Address Register - TMAR (2C)H

bit15

bit8

bit7

bit 0

MA2

MA1

MA0

READ

TIV

FABT

NOB

After reset (000F)H

When this register is written by the microprocessor, these different bits mean :

READ : READ MON MEMORY

READ=1, READ MON MEMORY.

READ=0, WRITE MON MEMORY.

MA 0/2 : TRANSMIT MONITOR ADDRESS

MA 0/2 :These bits define one of eight Monitor Channel if validated.

: This bit defines one of two GCI multiplexes.

G0 = 0, TDM4 is selected.

G0 = 1, TDM5 is selected.

NOB

: NUMBER OF BYTE to be transmitted

NOB = 1, One byte to transmit.

NOB = 0, Two bytes to transmit.

: Last byte

L = 1, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is the last.

L = 0, the word (or the byte) located in the Transmit Monitor Data Register (TMDR) is not the

last.

FABT

: FABT = 1, the current message is aborted by the transmitter.

TIV

: Timer interrupt is Validated

TIV = 1, Time Out alarm generates an interrupt when the timer has expired.

TIV = 0, Time Out alarm is masked.

If 8 bit microprocessor the Data (TMDR Register) is taken into account by the transmitter after writing bits

8 to 15 of this register.

Transmit Monitor Address Register (after reading)

bit15

bit8

bit7

bit 0

MA2

MA1

MA0

READ

ABT

NOBT EXE

IDLE

When this register is read by the microprocessor, these different bits mean :

READ, MA0/2, G0 have same definition as already described for the write register cycle.

IDLE

: When this bit is at ”1”, IDLE (all 1’s) is transmitted during the channel validation.

EXE

: EXECUTED

When this status bit is at ”1”, the command written previously by the microprocessor has been

executed and a new word can be stored in the Transmit Monitor Data Register (TMDR) by the

microprocessor.

When this bit is at ”0”, the command written previously by the microprocessor has not yet been

executed.

VIII - INTERNAL REGISTERS (continued)

STLC5465B

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