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STLC5465B 数据表(PDF) 92 Page - STMicroelectronics |
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STLC5465B 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 101 page  PRSR : Pseudo Random Sequence Recovered PRSR = 1,the Pseudo Random Sequence transmitted by the generatorhas been recovered by the analyzer. SFCO : Sequence Fault Counter Overload SFCO = 1, the Fault Counter has reached the value (00FF)H. VIII.30 - Interrupt Mask Register - IMR (3A)H bit15 bit8 bit7 bit 0 Nu Nu IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 After reset (FFFF)H IM13/0 : INTERRUPT MASK 0/7 When IM0 = 1, HDLC bit is masked. When IM1 =1, C/IRX bit is masked. When IM2 = 1, MRX bit is masked. When IM3 = 1, MTX bit is masked. When IM4 = 1, ICOV bit is masked When IM5 = 1, RxFWAR bit is masked. When IM6 = 1, RxFOV bit is masked. When IM7 = 1, TxFWAR bit is masked. When IM8 = 1, TxFOV bit is masked. When IM9 = 1, INTFWAR bit is masked. When IM10 = 1, INTFOV bit is masked. When IM11 = 1, TIM bit is masked. When IM12 = 1, PRSR bit is masked. When IM13 = 1, SFCO bit is masked. VIII.31 - Timer Register - TIMR (3C)H bit15 bit12 bit0 bit1 bit 0 S3 S2 S1 S0 MS9 MS8 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 MM1 MM0 0 to 15s 0 to 999ms 0 to 3x0.25ms After reset (0800)H id 512ms This programmable register indicates the time at the end of which the Watch Dog delivers logic ”1” on the pin WDO (which is an output) but only if the microprocessor does not reset the counter assigned (with the help of WDR bit of IDCR Identification and Dynamic Command Register) during the time defined by the Timer Register. The Timer Register and its counter can be used as a time base by the microprocessor. An interrupt (TIM) is generated at each period defined by the Timer Register if the microprocessor does not reset the counter with the help of WDR (bit of IDCR). The Watch Dog or the Timer is incremented by the Frame Synchronisation clock (TBFS=1) or by a submultiple of MCLK signal (TBFS=0; TBFS, bit of Interrupt Queue Size Register). When TSV=1{Time Stamping Validated (GCR)} this programmable register is not used. VIII.32 - Test Register - TR (3E)H bit15 bit8 bit7 bit 0 VIII - INTERNAL REGISTERS (continued) STLC5465B 92/101 |
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