STLC5465B datasheet(94/101 Pages) STMICROELECTRONICS

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IX.2 - Receive Descriptor

This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory

size only.

RDA+00

IBC

EOQ

Size Of the Buffer (SOB)

RDA+02

Not used

RBA High (8 bits)

RDA+04

Receive Buffer Address Low (16 bits)

RDA+06

Not used

NRDA High (8 bits)

RDA+08

Next Receive Descriptor Address Low (16 bits)

RDA+10

ABT

OVF

FCRC

Number of Bytes Received (NBR)

The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor

and read by the DMAC only. The 6th word located in shared memory in RDA+10 is written by the DMAC

only during the frame reception and read by the microprocessor.

SOB

: Size Of the Buffer associated to descriptor up to 2048 words (1 word = 2 bytes).

If SOB = 0, DMAC goes to next descriptor.

RBA

: Receive Buffer Address. LSB of RBA Low is at Zero mandatory.

RDA

: Receive Descriptor Address.

NRDA : Next Receive Descriptor Address. LSB of NRDA Low is at Zero mandatory.

NBR

: Number of Bytes Received (up to 4096).

IX.2.1 - Bits written by the Microprocessor only

IBC

: Interrupt if the buffer has been completed.

IBC=1, the DMAC generates an interrupt if the buffer has been completed.

EOQ

: End Of Queue.

EOQ=1, the DMAC stops immediately its reception generates an interrupt (HDLC = 1 in IR) and

waits a command from the HRCR (HDLC Receive Command Register).

EOQ=0, the DMAC continues.

IX.2.2 - Bits written by the Rx DMAC only

ABT

OVF

FCRC

Definition

The frame has been received without error. The end of frame is in this buffer.

The frame has been received with false CRC.

If NBR is different to 0, the buffer related to this descriptor is completed.The end

of frame is not in this buffer.

If NBR is equal to 0, the Rx DMAC is receiving a frame.

ABORT. The received frame has been aborted by the remote transmitter or the

local microprocessor.

OVERFLOW of FIFO. The received frame has been aborted.

The received frame had not an integer of bytes.

IX.2.3 - Receive Buffer

Each receive buffer is defined by its receive descriptor.

The maximum size of the buffer is 2048 words (1 word=2 bytes)

RBA

SECOND BYTE LOCATION

FIRST BYTE LOCATION

THIRD BYTE LOCATION

RBA+SOB-2

LAST BYTE LOCATION

AVAILABLE in the Receive Buffer

LAST - 1 BYTE LOCATION

AVAILABLE in the Receive Buffer

Note: for Motorola processors, a swap may be necessary to read/write the Receive Buffer.

IX - EXTERNAL REGISTERS (continued)

STLC5465B

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