STLC5465B datasheet(50/101 Pages) STMICROELECTRONICS

部件名	STLC5465B

功能描述	MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED

PDF	101 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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50 / 101 page

VI - MEMORY TIMING (continued)

Tota l Write Cycle

Ea ch s ignal from the MHDLC is high

impe dance outside this time if MBL = 0

1/f

NDS fr o m

µP

(or equivalent)

MASTE RCLOCK

a pplied to XTAL1 P in

ADM0/10

NWE

NOE

DM0/15

No te : S e e

MBL Definition

NRAS 0/3

NCAS 0/1

Tv/2

Figure 39 : Dynamic Memory Write Signals from the

Multi-HDLC

Symbol

Parameter

Min.

Typ.

Max.

Unit

f : Masterclock Frequency

MHz

Delay between beginning of cycle and NRAS Falling Edge

1/f

2/f

Delay between NRAS Falling Edge and NCAS Falling Edge

1/f

2/f

Delay between NCAS Falling Edge and NWE Rising Edge

1/f

2/f

Delay between NWE Rising Edge and end of cycle

1/f

2/f

Tv/2

Delay between NRAS Falling Edge and address change

1/2f

1/f

Data Valid after beginning of cycle (30 pF)

1/f

Note : Total Cycle : Tu + Tv + Tw + Tz

STLC5465B

50/101

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