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STMPE2403 数据表(PDF) 27 Page - STMicroelectronics |
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STMPE2403 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 63 page ![]() STMPE2403 Interrupt system 27/63 9.2 Interrupt Control Register (ICR) ICR register is used to configure the Interrupt Controller. It has a global enable interrupt mask bit that controls the interruption to the host. ICR_msb ICR_lsb Bit 15 14 13 12 11 10 9876543 2 1 0 Reserved IC2 IC1 IC0 R/W RRRRRR RRRRRRR RW RW RW Reset Value 000000 0000000 0 0 0 Table 24. Register description Bit Name Description 0IC[0] Global Interrupt Mask bit When this bit is written a ‘1’, it will allow interruption to the host. If it is written with a ‘0’, then, it disables all interruption to the host. Writing to this bit does not affect the IER value. 1IC[1] Output Interrupt Type ‘0’ = Level interrupt ‘1’ = Edge interrupt 2IC[2] Output Interrupt Polarity ‘0’ = Active Low / Falling Edge ‘1’ = Active High / Rising Edge |
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