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STMPE2403

Interrupt system

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9.4

Interrupt Status Register (ISR)

ISR register monitors the status of the interruption from a particular interrupt source to the

host. Regardless whether the IER bits are enabled or not, the ISR bits are still updated.

9.5

Interrupt Enable GPIO Mask Register (IEGPIOR)

IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source

to the host. The IEG[23:0] bits are the interrupt enable mask bits correspond to the

GPIO[23:0] pins.

ISR_msb

ISR_lsb

Bit

543

Reserved

IS8

IS7

IS6

IS5

IS4

IS3

IS2

IS1

IS0

R/W

Reset

Value

000

Table 26. Register description

Bits

Name

Description

8:0

IS[x]

Interrupt Status (where x = 8 to 0)

Read:

IS0 = Wake-up Interrupt Status

IS1 = Keypad Controller Interrupt Status

IS2 = Keypad Controller FIFO Overflow Interrupt Status

IS3 = Rotator Controller Interrupt Status

IS4 = Rotator Controller Buffer Overflow Interrupt Status

IS5 = PWM Channel 0 Interrupt Status

IS6 = PWM Channel 1 Interrupt Status

IS7= PWM Channel 2 Interrupt Status

IS8 = GPIO Controller Interrupt Status

Write:

A write to a IS[x] bit with a value of ‘1’ will clear the interrupt and a write with a

value of ‘0’ has no effect on the IS[x] bit.

Table 27. IEGPIOR register

Bit

765

IEGPIOR_msb

IEG-23

IEG -22 IEG -21 IEG -20 IEG -19 IEG -18 IEG -17 IEG -16

IEGPIOR _csb

IEG -15 IEG -14 IEG -13 IEG -12 IEG -11 IEG -10

IEG -9

IEG -8

IEGPIOR _lsb

IEG -7

IEG -6

IEG -5

IEG -4

IEG -3

IEG -2

IEG -1

IEG -0

Table 28. Register description

Name

Description

IEG[x]

Interrupt Enable GPIO Mask (where x = 23 to 0)

Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.

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