Operation

STWD100

8/25

Figure 4.

Open drain WDO output connection

2.3

Chip-enable input (EN)

All states mentioned in Section 2.1: Watchdog input (WDI) and Section 2.2: Watchdog

output (WDO) are valid under the condition that EN is in logical low state.

The behavior of EN is common to all versions (i.e. STWD100xP, STWD100xW, STWD100xX

and STWD100xY).

If the EN goes high anytime during normal operation, the WDO will go high as well, but the

minimum possible WDO pulse width is 10 µs (see Figure 10).

The pulses on the EN pin with a duration of at least 1 µs are detected and glitches shorter

than 100 ns are ignored.

2.4

Applications information

2.4.1

Interfacing to microprocessors with bidirectional reset pins

Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog

output, WDO. For example, if the WDO output is driven high and the micro wants to pull it

low, signal contention will result. To prevent this from occurring, connect a 4.7 k

Ω resistor

between the WDO output and the micro's reset I/O as in Figure 5.

GND

WDI

EN

+3.3 V

10 k

GND

AI12645a

+5.0 V

5 V System

WDO

STWD100