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ESDALC6V1F2 数据表(PDF) 3 Page - STMicroelectronics

部件名 ESDALC6V1F2
功能描述  Quad low capacitance Transil array for ESD protection
PDF  7 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ESDALC6V1F2 数据表(HTML) 3 Page - STMicroelectronics

  ESDALC6V1F2 Datasheet HTML 1Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 2Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 3Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 4Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 5Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 6Page - STMicroelectronics ESDALC6V1F2 Datasheet HTML 7Page - STMicroelectronics  
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ESDALC6V1F2
Characteristics
3/7
Figure 2.
Peak power dissipation versus
initial junction temperature
Figure 3.
Peak pulse power versus
exponential pulse duration
(Tj initial = 25° C)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
0
25
50
75
100
125
150
P
PP[T j initial] / PPP [T j initial=25°C]
Tj(°C)
10
100
1000
1
10
100
PPP(W)
tP(µs)
Figure 4.
Clamping voltage versus peak
pulse current (Tj initial = 25° C),
rectangular waveform tp = 2.5 µs).
Figure 5.
Capacitance versus reverse applied
voltage (typical values)
Figure 6.
Relative variation of the leakage
current versus junction
temperature (typical values)
0.1
1.0
10.0
100.0
0
5
10
15
20
25
30
35
40
45
50
IPP(A)
VCL(V)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
01
2
3
456
C(pF)
VR(V)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
25
50
75
100
125
I
R [Tj]/IR [Tj=25°C]
Tj(°C)



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