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LFSC 数据表(PDF) 13 Page - Lattice Semiconductor |
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LFSC 数据表(HTML) 13 Page - Lattice Semiconductor |
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13 / 237 page  2-9 Architecture Lattice Semiconductor LatticeSC/M Family Data Sheet Figure 2-7. Edge Clock Resources Precision Clock Divider Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower speed system clock from the high-speed edge clock. The block operates in a DIV2 or DIV4 mode and maintains a known phase relationship between the divided down clock and high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as pri- mary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via the edge clock network and is used for the rest of the I/O gearing logic. Figure 2-8. Clock Divider Circuit Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is SERDES SERDES Bank 1 Bank 5 Bank 4 Edge clock S/R S/R S/R S/R Divided clock Clock derived from selected PIOs, PLLs and routing LSR Register chain to synchronize LSR to clock input ELSR |
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