LFSC datasheet(21/237 Pages) LATTICE

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2-17

Architecture

Lattice Semiconductor

LatticeSC/M Family Data Sheet

high-speed interfaces in the LatticeSC devices. Figure 2-18 shows how differential receivers and drivers are

arranged between PIOs.

Figure 2-18. Differential Drivers and Receivers

PIO

The PIO contains ﬁve blocks: an input register block, output register block, tristate register block, update block, and

a control logic block. These blocks contain registers for both single data rate (SDR), double data rate (DDR), and

shift register operation along with the necessary clock and selection logic.

Input Register Block

The input register block contains delay elements and registers that can be used to condition signals before they are

passed to the device core. Figure 2-20 show the diagram of the input register block. The signal from the PURE-

SPEED I/O buffer (DI) enters the input register block and can be used for three purposes, as a source for the com-

binatorial (INDD) and clock outputs (INCK), the input into the SDR register/latch block and the input to the delay

block. The output of the delay block can be used as combinatorial (INDD) and clock (INCK) outputs, an input to the

DDR/Shift Register Block or an input into the SDR register block.

Input SDR Register/Latch Block

The SDR register/latch block has a latch and a register/latch that can be used in a variety of combinations to pro-

vide a registered or latched output (INFF). The latch operates off high-speed input clocks and latches data on the

positive going edge. The register/latch operates off the low-speed input clock and registers/latches data on the pos-

itive going edge. Both the latch and the register/latch have a clock enable input that is driven by the input clock

enable. In addition both have a variety of programmable options for set/reset including, set or reset, asynchronous

or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable.

The register and latch LSR inputs are driven from LSRI, which is generated from the PIO control MUX. The GSR

inputs are driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on

a PIO basis.

Input Delay Block

The delay block uses 144 tapped delay lines to obtain coarse and ﬁne delay resolution. These delays can be

adjusted during conﬁguration or automatically via DLL or AIL blocks. The Adaptive Input Logic (AIL) uses this delay

block to adjust automatically the delay in the data path to ensure that it has sufﬁcient setup and hold time.

The delay line in this block matches the delay line that is used in the 12 on-chip DLLs. The delay line can be set via

conﬁguration bits or driven from a calibration bus that allows the setting to be controlled either from one of the on-

chip DLLs or user logic. Controlling the delay from one of the on-chip DLLs allow the delay to be calibrated to the

DLL clock and hence compensated for the variations in process, voltage and temperature.

PIO D

PIO C

PADC "T"

PADD "C"

PIO A

PADA "T"

PIO B

PADB "C"

*Differential Driver only available on right and left of the device.

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