ST72334J2TASLASHXXX datasheet(28/150 Pages) STMICROELECTRONICS

部件名	ST72334J2TA/XXX

功能描述	8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces

PDF	150 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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8.2 RESET SEQUENCE MANAGER (RSM)

8.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 14:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of three

phases as shown in Figure 13:

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

The 4096 CPU clock cycle delay allows the oscil-

lator to stabilise and ensures that recovery has

taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 13. RESET Sequence Phases

Figure 14. Reset Block Diagram

RESET

DELAY

INTERNAL RESET

4096 CLOCK CYCLES

FETCH

VECTOR

fCPU

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

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