ST72334J2TASLASHXXX datasheet(39/150 Pages) STMICROELECTRONICS

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POWER SAVING MODES (Cont’d)

10.4.2 Halt Mode

The Halt mode is the lowest power consumption

mode of the MCU. It is entered by executing the

HALT instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see Section 13.2 "MAIN CLOCK CON-

TROLLER WITH REAL-TIME CLOCK TIMER

(MCC/RTC)" on page 53 for more details on the

MCCSR register).

The MCU can exit Halt mode on reception of either

a specific interrupt (see Table 6, “Interrupt Map-

ping,” on page 35) or a RESET. When exiting Halt

mode by means of a RESET or an interrupt, the

oscillator is immediately turned on and the 4096

CPU cycle delay is used to stabilize the oscillator.

After the start up delay, the CPU resumes opera-

tion by servicing the interrupt or by fetching the re-

set vector which woke it up (see Figure 24).

When entering Halt mode, the I bit in the CC regis-

ter is forced to 0 to enable interrupts. Therefore, if

an interrupt is pending, the MCU wakes immedi-

ately.

In Halt mode, the main oscillator is turned off caus-

ing all internal processing to be stopped, including

the operation of the on-chip peripherals. All periph-

erals are not clocked except the ones which get

their clock supply from another clock generator

(such as an external or auxiliary oscillator).

The compatibility of Watchdog operation with Halt

mode is configured by the “WDGHALT” option bit

of the option byte. The HALT instruction when ex-

ecuted while the Watchdog system is enabled, can

generate a Watchdog RESET (see Section 17.2

on page 143 for more details).

Figure 23. HALT Timing Overview

Figure 24. Halt Mode Flowchart

Notes:

1. WDGHALT is an option bit. See OPTION

BYTES section for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from Halt mode (such as external interrupt). Refer

to Table 6, “Interrupt Mapping,” on page 35 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 4)

4096 CPU CLOCK CYCLE

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

(MCCSR.OIE=0)

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