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ST72334J2TA/XXX 数据表(PDF) 49 Page - STMicroelectronics |
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ST72334J2TA/XXX 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 150 page ![]() ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 49/150 MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h) Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the PF1 pin beep capability. The beep output signal is available in Active Halt mode but has to be disabled to reduce the con- sumption. Bit 3:2 = Reserved Must always be cleared Bit 1 = SSM SS mode selection It is set and cleared by software. 0: Normal mode - SS uses information coming from the SS pin of the SPI. 1: I/O mode, the SPI uses the information stored into bit SSI. Bit 0 = SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software. Table 11. Miscellaneous Register Map and Reset Values 7 0 - - BC1 BC0 - - SSM SSI Beep mode with fOSC=16MHz BC1 BC0 Off 0 0 ~2 kHz Output Beep signal ~50% duty cycle 0 1 ~1 kHz 1 0 ~500 Hz 1 1 Address (Hex.) Register Label 7 6 5 4 3 2 1 0 0020h MISCR1 Reset Value IS11 0 IS10 0 MCO 0 IS21 0 IS20 0 CP1 0 CP0 0 SMS 0 0040h MISCR2 Reset Value 0 0 BC1 0 BC0 0 0 0 SSM 0 SSI 0 |
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