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STE2007 数据表(PDF) 14 Page - STMicroelectronics |
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STE2007 数据表(HTML) 14 Page - STMicroelectronics |
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14 / 62 page ![]() Electrical characteristics STE2007 14/62 Figure 3. Driver TxData Mode AC timing characteristics 3.5.1 Reset timing Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. Hi±Z Status T1 T2 T3 T4 Tx Tx Rx Command Command Hi±Z SCLK Hi±Z Hi±Z Timing B Timing A Timing A Timing B !CS !CS MCU TxData Driver TxData SCLK SCLK Driver TxData MCU TxData MCU Data direction Driver TxData MCU TxData Driver SDA direction in out out in Driver SDA direction T5 D/C 1/2 SCLK 1/2 SCLK Table 14. Reset timing Symbol Signal Description Min. Max. Unit trs !RES Reset time 2500 ns trw !RES Reset low pulse width (for valid reset) 2500 trj !RES Reset rejection (for noise spike) 1000 |
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