STE2007 datasheet(22/62 Pages) STMICROELECTRONICS

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Interface

STE2007

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Figure 13.

4-lines SPI Data transfer pause

4.2.2

Driver TxData Mode (read mode)

Throughout SDA line is possible to read some registers value (ID Numbers, Status byte,

temperature).

SDA (output Driver) is in High impedance in steady state and during data write.

Figure 14.

4-lines SPI 8-Bit read cycle

4.3

I2C Bus

The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast

(400kHz Clock) and High Speed Mode (3.4MHz).

This bus is intended for communication between different ICs. It consists of two lines: one

bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL

lines must be connected to a positive supply voltage via an active or passive pull-up.

The following protocol has been defined:

–

Data transfer may be initiated only when the bus is not busy.

–

During data transfer, the data line must remain stable whenever the clock line is

high. Changes in the data line while the clock line is high will be interpreted as a

Start or Stop Data Transfer condition (see below).

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

LR0191

D/!C

!CS

SDA

SCL

COMMAND/PARAMETER

Pause

LR0255

!CS

SCL

Read Command

DATA

SDA

(Input)

SDA

(Output)

High Z

MCU Data Tx Start

LCD Driver Data Tx Start

Next Command

D!C

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