STE2007 datasheet(28/62 Pages) STMICROELECTRONICS

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Display Data RAM (DDRAM)

STE2007

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Display Data RAM (DDRAM)

5.1

DDRAM and Page/column address circuit

The DDRAM stores pixel data for LCD. It is a 68–row (8 page by 8 bits +4) by 96–column

addressable array. D7 to D0 display data from MCU corresponds to the LCD common

direction. ”0” bit in DDRAM is a OFF–dot on display and ”1” bit in DDRAM is displayed as

ON–dot on display.

Figure 21.

DDRAM vs. display on LCD

Each pixel can be selected when page address and column address are specified. The

MCU issues Page address set command to change the page and access to another page.

In DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are

valid.

The DDRAM column address is specified by Column address set command.

The specified column address is automatically incremented by +1 when a Display data write

command is entered. After the last column address (5Fh), column address returns to 00h

and page address incremented by +1. After the very last address (column=5Fh, page=8h),

both column address and page address return to 00h (column address=00h, page

address=0h).

Figure 22.

Column address in normal mode

COM0

COM1

COM2

COM3

COM4

±±

DDRAM

Display on LCD

192 193 194

288 289 290

384 385 386

480 481 482

190 191

286 287

382 383

478 479

574 575

00H 01H 02H

5EH 5FH

Data

Page address

Column address

576 577 578

672 673 674

768 769 770

670 671

766 767

862 863

Data for page address 0H to 07H

Data for page address 8H

LSBit

MSBit

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