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STW4811MBRA/LF 数据表(PDF) 61 Page - STMicroelectronics |
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STW4811MBRA/LF 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 86 page ![]() Electrical and timing characteristics STw4811M/STw4811N 60/85 VIO_VMEM regulator in sleep mode (SLEEP=’1’) VBAT Input power supply Battery voltage 2.7 3.6 4.8 V VRIPPLE Output ripple 10 mVpp LIR Line regulation VBAT: [2.7; 4.8]V 10 mV LDR Load regulation IOUT: [0.1; 5] mA 10 mV IOUT Output current 5 mA PEFF Power efficiency VBAT = 3.6 V IOUT = [0.1; 5] mA 85 % IQ Quiescent current IOUT = 0 mA 20 µA LIRT Transient line regulation ΔVBAT = 300 mV tR = tF = 10 µs 2 mV 1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. Guaranteed by design Table 40. VIO_VMEM DC/DC step-down converter (continued) Symbol Description Test conditions Min. Typ. Max. Units |
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