STW4811MBRASLASHLF datasheet(39/86 Pages) STMICROELECTRONICS

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Functional description

STw4811M/STw4811N

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4.2.6

IT generation

STw4811 has three interrupt balls:

IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is

plugged this interrupt is activated to wake up the host or the modem, depends of application

(open drain, active low).

By default this feature is available independently of PON level, it can be masked when

PON = 1 by ‘mask_it_wake_up’ bit of

Configuration 2 register (see Table 28)

USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor.

Independently of PWREN ball state, this ball goes to low level if an USB interrupt source is

detected. In sleep mode, PWREN = 0, an interrupt source is detected only if unmasked

before PWREN goes to low level.

VDDOK: This ball has two functions:

- When high, it indicates that VIO_VMEM and VCORE output voltages are within the right

range and that the device internal temperature is below the maximum allowed temperature.

- When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated

properly or PWREN = “0”, or that the temperature is above the allowed threshold (see

Thermal shut-down section), ‘it_warm’ bit of Configuration 1 register is the temperature

interruption source (see

Table 18).

4.2.7

Clock switching and control

This block generates the clock used by the DC/DC converter (USB charge pump, step-down

VIO_VMEM and step-down VCORE). STw4811 is able to sustain the master clock

frequencies of 26 MHz, 19.2MHz and 13 MHz. If the clock is not detected the internal

oscillator is automatically selected.

STw4811 allows customers to use the internal clock issued from the internal oscillator to

switch the SMPS and charge pump; or, they can provide an external clock and connect it to

the master clock input. If it is not necessary, it is recommended to run the device on the

internal clock. Nevertheless, if the external clock is used, this clock has some constraints:

–

the master-clk must be provided each time the device is in high power mode.

When the device changes from sleep mode to high power mode the master-clk

must be active before the device is in high power mode (the master-clk must be

available and stable when PWREN pin goes to high level).

–

the only way to stop the use of the master_clk, in HPM mode, is to restart the

device with the OFF/ON sequence on PON (PON = 1 then 0 then 1)

Note:

When present the Master clock should remain connected up to sleep mode.

STW4811MBRA/LF 数据表(PDF) 39 Page - STMicroelectronics

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