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STPC12GDYC 数据表(PDF) 8 Page - STMicroelectronics |
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STPC12GDYC 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 111 page  GENERAL DESCRIPTION 8/111 Issue 1.0 - July 24, 2002 1.7. CLOCK TREE The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. The speed of the PLLs is either fixed (DEVCLK), either programmable by strap option (HCLK) either programmable by software (DCLK, MCLK). When in synchronized mode, MCLK speed is fixed to HCLKO speed and HCLKI is generated from MCLKI. Figure 1-2. STPC Atlas clock architecture Kbd/Mouse IPC SDRAM controller North Bridge 14.31818 MHz XTALO XTALI OSC14M ISACLK 1/4 DEVCLK DEVCLK (24MHz) PLL (14MHz) 1/2 UARTs HCLK PLL PCICLKI PCICLKO South Bridge PWM 1/2 1/3 HCLK DCLK PLL MCLK PLL DCLK MCLKI MCLKO USB CRTC,Video,TFT CPU x2 VCLK 48MHz // Port 1/4 1/2 1/26 1/6 VIP GE, LDE, AFE PCMCIA Local Bus Host ISA HCLKI HCLKO |
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