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STPC12GDYC 数据表(PDF) 54 Page - STMicroelectronics

部件名 STPC12GDYC
功能描述  X86 Core PC Compatible System-on-Chip for Terminals
PDF  111 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPC12GDYC 数据表(HTML) 54 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
54/111
Issue 1.0 - July 24, 2002
4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-8 and Table 4-14 list the AC characteris-
tics of the ISA interface.
Figure 4-8 ISA Cycle (ref Table 4-14)
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Valid AENx
Valid Address
Valid Address, SBHE*
V.Data
VALID DATA
54
28
26
64
59
58
55
28
23
61
48
47
26
23
57
27
24
42
41
10
11
34
33
3
22
56
29
25
9
18
2
12
38
37
15
14
13
12
ALE
AEN
LA [23:17]
SA [19:0]
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
Table 4-14. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
2
LA[23:17] valid before ALE# negated
5T
Cycles
3
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
5T
Cycles
3b Memory access to 8-bit ISA Slave
5T
Cycles
9
SA[19:0] & SBHE valid before ALE# negated
1T
Cycles
10
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
2T
Cycles
10b Memory access to 8-bit ISA Slave
2T
Cycles
10
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c Memory access to 16-bit ISA Slave
2T
Cycle
Note: The signal numbering refers to Table 4-8



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