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STPC12GDYC 数据表(PDF) 43 Page - STMicroelectronics |
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STPC12GDYC 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 111 page  ELECTRICAL SPECIFICATIONS Issue 1.0 - July 24, 2002 43/111 4. ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Atlas. 4.2. ELECTRICAL CONNECTIONS 4.2.1. POWER/GROUND CONNECTIONS/ DECOUPLING Due to the high frequency of operation of the STPC Atlas, it is necessary to install and test this device using standard high frequency techniques. The high clock frequencies used in the STPC Atlas and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VSS and VDD pins. 4.2.2. UNUSED INPUT PINS No unused input pin should be left unconnected unless they have an integrated pull-up or pull- down. Connect active-low inputs to VDD through a 20 k Ω (±10%) pull-up resistor and active-high inputs to VSS. For bi-directionnal active-high inputs, connect to VSS through a 20 k Ω (±10%) pull-up resistor to prevent spurious operation. 4.2.3. RESERVED DESIGNATED PINS Pins designated as reserved should be left dis- connected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3. ABSOLUTE MAXIMUM RATINGS The following table lists the absolute maximum ratings for the STPC Atlas device. Stresses beyond those listed under Table 4-1 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those specified in section "Operating Conditions". Exposure to conditions beyond those outlined in Table 4-1 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 4-1) may also result in reduced useful life and reliability. 4.3.1. 5V TOLERANCE The STPC is capable of running with I/O systems that operate at 5 V such as PCI and ISA devices. Certain pins of the STPC tolerate inputs up to 5.5 V. Above this limit the component is likely to sustain permanent damage. All 5 volt tolerant pins are outlined in Table 2-3 Buffer Type Descriptions. Note 1: The figures specified apply to the Tcase of a STPC device that is soldered to a board, as detailed in the Design Guidelines Section, for Commercial and In- dustrial temperature ranges. Table 4-1. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units VDDx DC Supply Voltage -0.3 4.0 V VCORE DC Supply Voltage for Core -0.3 2.7 V VI, VO Digital Input and Output Voltage -0.3 VDD + 0.3 V V5T 5Volt Tolerance -0.3 5.5 V VESD ESD Capacity (Human body mode) - 2000 V TSTG Storage Temperature -40 +150 °C TOPER Operating Temperature (Note 1) 0 +85 °C -40 +115 °C PTOT Maximum Power Dissipation (package) - 4.8 W |
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