STPC12GDYC datasheet(105/111 Pages) STMICROELECTRONICS

105 / 111 page

DESIGN GUIDELINES

Issue 1.0 - July 24, 2002

105/111

6.5. DEBUG METHODOLOGY

In order to bring a STPC-based board to life with

the best efficiency, it is recommended to follow the

check-list described in this section.

6.5.1. POWER SUPPLIES

In parallel with the assembly process, it is useful to

get a bare PCB to check the potential short-

circuits between the various power and ground

planes. This test is also recommended when the

first boards are back from assembly. This will

avoid bad surprises in case of a short-circuit due

to a bad soldering.

When the system is powered, all power supplies,

including the PLL power pins must be checked to

be sure the right level is present. See Table 4-2 for

the exact supported voltage range:

VDD_CORE: 2.5V

VDD_xxxPLL: 2.5V

VDD: 3.3V

6.5.2. BOOT SEQUENCE

6.5.2.1. Reset input

The checking of the reset sequence is the next

step. The waveform of SYSRSTI# must complies

with the timings described in Figure 4-3. This

signal must not have glitches and must stay low

until the 14.31818MHz output (OSC14M) is at the

right

frequency

and

the

strap

options

are

stabilized to a valid configuration.

In case this clock is not present, check the 14MHz

oscillator stage (see Figure 6-3).

6.5.2.2. Strap options

The STPC has been designed in a way to allow

configurations for test purpose that differs from the

functional configuration. In many cases, the

troubleshootings at this stage of the debug are the

resulting of bad strap options. This is why it is

mandatory to check they are properly setup and

sampled during the boot sequence.

The list of all the strap options is summarized at

the beginning of Section 3.

6.5.2.3. Clocks

Once OSC14M is checked and correct, the next

signals to measure are the Host clock (HCLK),

PCI clocks (PCI_CLKO, PCI_CLKI) and Memory

clock (MCLKO, MCLKI).

HCLK must run at the speed defined by the

corresponding strap options (see Table 3-1). In x2

CPU clock mode, this clock must be limited to

66MHz.

PCI_CLKI and PCI_CLKO must be connected as

described in Figure 6-19 and not be higher than

33MHz. Their speed depends on HCLK and on

the divider ratio defined by the MD[4] and MD[17]

strap options as described in Section 3.

To ensure a correct behaviour of the device, the

PCI deskewing logic must be configured properly

by the MD[7:6] strap options according to Section

3. For timings constraints, refers to Section 4.

MCLKI and MCLKO must be connected as

described in Figure 6-3 to Figure 6-5 depending

on the SDRAM implementation. The memory

clock

must

run

HCLK

speed

when

synchronous mode and must not be higher than

90MHz in any case. The MCLK interface will run

100MHz operation is possible but board layout is

so critical that 90MHz maximum operation is

recommended.

6.5.2.4. Reset output

If SYSRSTI# and all clocks are correct, then the

SYSRSTO# output signal should behave as

described in Figure 4-3.

6.5.3. ISA MODE

Prior to check the ISA bus control signals,

PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK

must be running properly. If it is not the case, it is

probably because one of the previous steps has

not been completed.

6.5.3.1. First code fetches

When booting on the ISA bus, the two key signals

to check at the very beginning are RMRTCCS#

and FRAME#.

The first one is a Chip Select for the boot flash

and is multiplexed with the IDE interface. It should

toggle together with ISAOE# and MEMRD# to

fetch the first 16 bytes of code. This corresponds

to the loading of the first line of the CPU cache.

In case RMRTCCS# does not toggle, it is then

necessary to check the PCI FRAME# signal.

Indeed the ISA controller is part of the South

Bridge and all ISA bus cycles are visible on the

PCI bus.

If there is no activity on the PCI bus, then one of

the previous steps has not been checked properly.

If there is activity then there must be something

conflicting on the ISA bus or on the PCI bus.

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