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STPC4EEBC 数据表(PDF) 35 Page - STMicroelectronics

部件名 STPC4EEBC
功能描述  X86 Core PC Compatible Information Appliance System-on-Chip
PDF  93 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPC4EEBC 数据表(HTML) 35 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
Release 1.5 - January 29, 2002
35/93
Note 1: PCI clock at 33MHz
Table 4-5. VGA RAMDAC Power Consumption
DCLK
(MHz)
DAC mode
(State)
PMax (mW)
VDD_DAC = 2.45V
VDD_DAC = 2.7V
-
Shutdown
0
0
6.25 - 135
Active
150
180
Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
Mode
DCLK
(MHz)
PMU
(State)
PMax (W)
V2.5V=2.45V
V2.5V=2.7V
66
66 (x1)
66
SYNC
Stopped
Stop Clock
0.6
0.9
Full Speed
1.4
1.8
135
Stop Clock
0.9
1.2
Full Speed
1.7
2.3
100
100 (x1)
100
SYNC
Stopped
Stop Clock
0.8
1.1
Full Speed
1.5
2.0
135
Stop Clock
1.5
1.9
Full Speed
2.1
2.7
66
133 (x2)
66
SYNC
Stopped
Stop Clock
0.7
0.9
Full Speed
1.7
2.1
135
Stop Clock
0.9
1.2
Full Speed
1.9
2.5
66
133 (x2)
100
ASYNC
Stopped
Stop Clock
0.8
1.1
Full Speed
1.6
2.1
135
Stop Clock
1.5
1.9
Full Speed
2.3
2.9
Table 4-7. 3.3V Power Consumptions (VDD)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
DCLK
(MHz)
PMU
(State)
PMax
(mW)
66
66 (x1)
66
6.26
Full Speed
90
135
160
100
100 (x1)
100
6.26
Full Speed
115
135
180
66
133 (x2)
66
6.26
Full Speed
100
135
165
66
133 (x2)
100
6.26
Full Speed
115
135
180
Table 4-8. PLL Power Consumptions
PLL name
PMax (mW)
VDD_PLL = 2.45V
VDD_PLL = 2.7V
VDD_DCLK_PLL
5
10
VDD_DEVCLK_PLL
5
10
VDD_HCLKI_PLL
5
10
VDD_HCLKO_PLL
5
10
VDD_MCLKI_PLL
5
10
VDD_MCLKO_PLL
5
10
VDD_PCICLK_PLL
5
10



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