 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STPC4EEBC 数据表(PDF) 46 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STPC4EEBC 数据表(HTML) 46 Page - STMicroelectronics |
|
|
46 / 93 page  ELECTRICAL SPECIFICATIONS 46/93 Release 1.5 - January 29, 2002 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 6T Cycles 41b Memory access to 8-bit ISA Slave 12T Cycles 41c I/O access to 16-bit ISA Slave 6T Cycles 41d I/O access to 8-bit ISA Slave 12T Cycles 42 SA[19:0] SBHE valid to read data valid 42b Memory access to 16-bit ISA Slave Standard cycle 4T Cycles 42e Memory access to 8-bit ISA Slave Standard cycle 10T Cycles 42h I/O access to 16-bit ISA Slave Standard cycle 4T Cycles 42l I/O access to 8-bit ISA Slave Standard cycle 10T Cycles 47 MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated 47a Memory access to 16-bit ISA Slave 2T Cycles 47b Memory access to 8-bit ISA Slave 5T Cycles 47c I/O access to 16-bit ISA Slave 2T Cycles 47d I/O access to 8-bit ISA Slave 5T Cycles 48 MEMR#, SMEMR#, IOR# asserted to read data valid 48b Memory access to 16-bit ISA Slave Standard Cycle 2T Cycles 48e Memory access to 8-bit ISA Slave Standard Cycle 5T Cycles 48h I/O access to 16-bit ISA Slave Standard Cycle 2T Cycles 48l I/O access to 8-bit ISA Slave Standard Cycle 5T Cycles 54 IOCHRDY asserted to read data valid 54a Memory access to 16-bit ISA Slave 1T(R)/2T(W) Cycles 54b Memory access to 8-bit ISA Slave 1T(R)/2T(W) Cycles 54c I/O access to 16-bit ISA Slave 1T(R)/2T(W) Cycles 54d I/O access to 8-bit ISA Slave 1T(R)/2T(W) Cycles 55a IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# negated 1T Cycles 55b IOCHRY asserted to MEMR#, SMEMR# negated (refresh) 1T Cycles 56 IOCHRDY asserted to next ALE# asserted 2T Cycles 57 IOCHRDY asserted to SA[19:0], SBHE invalid 2T Cycles 58 MEMR#, IOR#, SMEMR# negated to read data invalid 0T Cycles 59 MEMR#, IOR#, SMEMR# negated to data bus float 0T Cycles 61 Write data before MEMW# asserted 61a Memory access to 16-bit ISA Slave 2T Cycles 61b Memory access to 8-bit ISA Slave (Byte copy at end of start) 2T Cycles 61 Write data before SMEMW# asserted 61c Memory access to 16-bit ISA Slave 2T Cycles 61d Memory access to 8-bit ISA Slave 2T Cycles 61 Write Data valid before IOW# asserted 61e I/O access to 16-bit ISA Slave 2T Cycles 61f I/O access to 8-bit ISA Slave 2T Cycles 64a MEMW# negated to write data invalid - 16-bit 1T Cycles 64b MEMW# negated to write data invalid - 8-bit 1T Cycles 64c SMEMW# negated to write data invalid - 16-bit 1T Cycles 64d SMEMW# negated to write data invalid - 8-bit 1T Cycles Table 4-13. ISA Bus AC Timing Name Parameter Min Max Units Note: The signal numbering refers to Table 4-7 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
