M41ST87WMX6 datasheet(21/48 Pages) STMICROELECTRONICS

21 / 48 page

M41ST87Y, M41ST87W

Operating modes

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2.6.6

Tamper detect sampling (TDS1 and TDS2)

This bit selects between a 1Hz sampling rate or constant monitoring of the tamper input

pin(s) to detect a tamper event when the normally closed switch mode is selected. This

allows the user to reduce the current drain when the TEBX bit is enabled while the device is

in battery backup (see Table 4 on page 22 and Figure 16 on page 22). Sampling is disabled

if the TCMX bit is set to logic '1' (Normally Open). In this case the state of the TDSX bit is a

“Don’t care.”

Note:

The crystal oscillator must be “on” for sampling to be enabled.

2.6.7

Tamper current high/tamper current low (TCHI/TCLO1 and

TCHI/TCLO2)

This bit selects the strength of the internal pull-up or pull-down used during the sampling of

the normally closed condition. The state of the TCHI/TCLOX bit is a “Don’t care” for normally

open (TCMX = '1') mode (see Figure 17 on page 23).

2.6.8

RAM clear (CLR1 and CLR2)

When either of these bits and the TEBX bit are set to a logic '1,' the internal 128 bytes of

user RAM (see Figure 14 on page 20) will be cleared to all zeros in the event of a tamper

condition. The 128 bytes of user RAM will be deselected (invalid data will be read) until the

corresponding TEBX bit is reset to '0.'

2.6.9

RAM clear external (CLR1EXT and CLR2EXT)

When either of these bits are set to a logic '1' and the TEBX bit is also set to logic '1,' the

external SRAM will be cleared and the RST output enabled (see Figure 14 on page 20 and

Figure 19 on page 24).

Note:

The reset output resulting from a tamper event will be the same as a reset resulting from a

power-down condition, a watchdog time-out, or a manual reset (RSTIN1 or RSTIN2).

This is accomplished by forcing TPCLR high, which if used to control the inhibit pin of the DC

regulator (see Figure 19 on page 24) will also switch off VOUT, depriving the external SRAM

of power to the VCC pin. VOUT will automatically be disconnected from the battery if the

tamper occurs during battery back-up (see Figure 18 on page 23). By inhibiting the DC

regulator, the user will also prevent other inputs from sourcing current to the external SRAM,

allowing it to retain data.

The user may optionally connect an inverting charge pump to the VCC pin of the external

SRAM (see Figure 19 on page 24). Depending on the process technology used for the

manufacturing of the external SRAM, clearing the memory may require varying durations of

negative potential on the VCC pin. This device configuration will allow the user to program

the time needed for their particular application. Control Bits CLRPW0 and CLRPW1

determine the duration TPCLR will be enabled (see Figure 18 on page 23 and Table 5 on

page 24).

Note:

When using the inverting charge pump, the user must also provide isolation in the form of

two additional small-signal power MOSFETs. These will isolate the VOUT pin from both the

negative voltage generated by the charge pump during a tamper condition, and from being

pulled to ground by the output of the charge pump when it is in shut-down mode (SHDN =

logic low). The gates of both MOSFETs should be connected to TPCLR as shown in

Figure 19 on page 24. One n-channel enhancement MOSFET should be placed between

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