Operating modes

M41ST87Y, M41ST87W

24/48

Table 5.

Tamper detect timing

Figure 19.

RAM clear hardware hookup

1.

Most inverting charge pumps drive OUT to ground when device shut down is enabled (SHDN = logic low). Therefore, an n-

2.

2.7

Tamper detection operation

The tamper pins are triggered based on the state of an external switch. Two switch mode

options are available, “normally open” or “normally closed,” based on the setting of the

Symbol

Parameter

CLRPW

1

CLRPW

0

Min

Typ

Max

Unit

(1)

1.

With input capacitance = 70 pF and resistance = 50

Ω.

Tamper RAM clear ext delay

X

X

2.

1.5

2.0

ms

Tamper clear timing

00

1

s

01

4

s

10

8

s

11

16

s

AI07804

EX

SCL

M41ST87Y/W

WDI

RSTIN1

RSTIN2

IRQ/OUT

SQW/FT

RST

SDA

CAP+ CAP–

Inverting

Charge

Pump

SHDN

OUT

IN

Pushbutton

Reset

Low-Power

SRAM

Negative Output

(–1 x VIN)

E

To RST

To LED Display

(2)

(1)

To NMI

To INT

To 32kHz

Inhibit

5V

Regulator