33742S datasheet(23/70 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 33742 and the 33742S are system basis chips (SBCs)

dedicated to automotive applications. Their functions include

the following:

• One fully protected 5.0V voltage regulator with 200mA

total output current capability available at the VDD pin.

• VDD regulator under-voltage reset function,

programmable window or time-out software watchdog

function.

• Internal driver (V2) for an external series pass transistor

to implement a second 5.0V voltage regulator.

• Two running modes: Normal and Standby modes set by

the system microcontroller.

• Sleep and Stop modes low power operating modes to

reduce an application’s current consumption while

providing a wake-up capability from the CAN interface,

L3:L0 wake-up inputs, or from a timer wake-up.

• Programmable wake-up input and cyclic sense wake-

ups.

• CAN high-speed physical bus interface with TXD and

RXD fault diagnostic capability and enhanced

protection features.

• An SPI interface for use in communicating with a MCU

and Interrupt outputs to report SBC status, perform

diagnostics, and report wake-up events.

FUNCTIONAL PIN DESCRIPTION

RECEIVE AND TRANSMIT DATA (RXD AND TXD)

The RXD and TXD pins (receive data and transmit data

pins, respectively) are connected to a microcontroller’s CAN

protocol handler. TXD is an input and controls the CANH and

CANL line state (dominant when TXD is LOW, recessive

when TXD is HIGH). RXD is an output and reports the bus

state (RXD LOW when CAN bus is dominant, HIGH when

CAN bus is recessive). The RXD terminal is a push-pull

structure between the V2 pin and GND.

Voltage Digital Drain (VDD)

The VDD pin is the output pin of the 5.0V internal regulator.

It can deliver up to 200mA. This output is protected against

over-current and over-temperature. It includes an over-

temperature pre-warning flag, which is set when the internal

regulator temperature exceeds 130°C typical. When the

temperature exceeds the over-temperature shutdown (170°C

typical), the regulator is turned off.

VDD includes an under-voltage reset circuitry, which sets

the RST pin LOW when VDD is below the under-voltage reset

threshold.

RESET OUTPUT (RST)

The Reset pin RST, is an output that is set LOW when the

device is in reset mode. The RST pin is set HIGH when the

device is not in reset mode. RST includes an internal pullup

current source. When RST is LOW, the sink current capability

is limited, allowing RST to be shorted to 5.0V for software

debug or software download purposes.

INTERRUPT OUTPUT (INT)

The Interrupt pin INT, is an output that is set LOW when an

interrupt occurs. INT is enabled using the Interrupt Register

(INTR). When an interrupt occurs, INT stays LOW until the

interrupt source is cleared.

INT output also reports a wake-up event by a 10

μs typical

pulse when the device is in Stop mode.

VOLTAGE SOURCE 2 (V2)

The V2 pin is the input sense for the V2 regulator. It is

connected to the external series pass transistor. V2 is also

the 5.0V supply of the internal CAN interface. It is possible to

connect V2 to an external 5.0V regulator or to the VDD output

when no external series pass transistor is used. In this case,

the V2CTRL pin must be left open. Refer to Figure 31, SBC

Typical Application Schematic, page 57.

VOLTAGE SOURCE 2 CONTROL (V2CTRL)

The V2CTRL pin is the output drive pin for the V2 regulator

connected to the external series pass transistor.

VOLTAGE SUPPLY (VSUP)

The VSUP pin is the battery supply input of the device.

HIGH-SIDE OUTPUT (HS)

The HS pin is the internal high side driver output. It is

internally protected against over-current and over-

temperature.

LEVEL 0-3 INPUTS (L0: L3)

The L0:L3 pins can be connected to contact switches or

the output of other ICs for external inputs. The input states

can be read by SPI. These inputs can be used as wake-up

events for the SBC when operating in the Sleep or Stop

mode.

CAN HIGH AND CAN LOW OUTPUTS

(CANH AND CANL)

The CAN High and CAN Low pins are the interfaces to the

CAN bus lines. They are controlled by TXD input level, and

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