33982 datasheet(23/35 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33982

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DEVICE REGISTER ADDRESSING

The following section describes the possible register

addresses and their impact on device operation.

Address x000—Status Register (STATR)

The STATR register is used to read the device status and

the various configuration register contents without disrupting

the device operation or the register contents. The register bits

D2, D1, and D0 determine the content of the first eight bits of

SO data. In addition to the device status, this feature provides

the ability to read the content of the OCR, SOCHLR,

CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers.

(Refer to the section entitled Serial Output Communication

(Device Status Return Data) beginning on page 25.)

Address x001—Output Control Register (OCR)

The OCR register allows the MCU to control the output

through the SPI. Incoming message bit D0 (IN_SPI) reflects

the desired states of the high-side output: a Logic [1] enables

the output switch and a Logic [0] turns it OFF. A Logic [1] on

message bit D1 enables the Current Sense (CSNS) pin. Bits

D2 and D3 must be Logic [0]. Bit D7 is used to feed the

watchdog if enabled.

Address x010—Select Overcurrent High and Low

The SOCHLR register allows the MCU to configure the

output over-current low and high detection levels,

respectively. In addition to protecting the device, this slow

blow fuse emulation feature can be used to optimize the load

requirements to match system characteristics. Bits D2:D0

are used to set the over-current low detection level to one of

eight possible levels as defined in Table 10. Bit D3 is used to

set the over-current high detection level to one of two levels

as defined in Table 11.

Address x011—Current Detection Time and Open Load

The CDTOLR register is used by the MCU to determine

the amount of time the device will allow an over-current low

condition before output latches OFF occurs. Bits D1 and D0

allow the MCU to select one of four fault blanking times

defined in Table 12. Note that these timeouts apply only to

the over-current low detection levels. If the selected over-

current high level is reached, the device will latch off within

μs.

A Logic [1] on bit D2 disables the over-current low

(CD_dis) detection timeout feature. A Logic [1] on bit D3

disables the open load (OL) detection feature.

Address x100—Direct Input Control Register (DICR)

The DICR register is used by the MCU to enable, disable,

or configure the direct IN pin control of the output. A Logic [0]

on bit D1 will enable the output for direct control by the IN pin.

A Logic [1] on bit D1 will disable the output from direct control.

While addressing this register, if the input was enabled for

Table 9. Serial Input Address and Configuration Bit Map

Serial Input Data

D7 D6 D5 D4

STATR

SOA2

SOA1

SOA0

OCR

CSNS

IN_SPI

SOCHLR

SOCH SOCL2 SOCL1 SOCL0

CDTOLR

1 OL_dis CD_dis OCLT1

OCLT0

DICR

FAST

CSNS

high

IN dis

A/O

OSDR

OSD2

OSD1

OSD0

WDR

WD1

WD0

NAR

UOVR

UV_dis OV_dis

TEST

Freescale Internal Use (Test)

x = Don’t care.

Table 10. Overcurrent Low Detection Levels

SOCL2

(D2)

SOCL1

(D1)

SOCL0

(D0)

Over-current Low Detection

(Amperes)

Table 11. Over-current High Detection Levels

SOCH (D3)

Over-current High Detection

(Amperes)

150

100

Table 12. Over-current Low Detection Blanking Time

OCLT[1:0]

Timing

155ms

10ms

1.2ms

150

μs

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