Device operation

M24C16, M24C08, M24C04, M24C02, M24C01

16/34

Figure 9.

Read mode sequences

1.

be identical.

3.7

Read operations

Read operations are performed independently of the state of the Write Control (WC) signal.

The device has an internal address counter which is incremented each time a byte is read.

3.7.1

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 9) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI01942

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

ACK

R/W

ACK

ACK

ACK

NO ACK

R/W

NO ACK

ACK

ACK

R/W

ACK

ACK

R/W

ACK

NO ACK