HD404324FS datasheet(71/103 Pages) RENESAS

71 / 103 page

HD404054 Series/HD404094 Series

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a

spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit

clock error of this type can be detected as shown in figure 52.

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse

by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and

transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is

entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005)

changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the

serial 1 interrupt request flag is set again, and therefore the error can be detected.

Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit

clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode

• Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from

transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS

instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set.

To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution

must be programmed to be executed after confirming that the

SCK

1 pin is at 1, that is, after executing

the input instruction to port R4.

HD404324FS 数据表(PDF) 71 Page - Renesas Technology Corp