STV2000

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OPERATING DESCRIPTION (continued)

1.8 Sync Processor Output

The sync processor indicates whether 1st PLL is locked to an incoming horizontal sync or not. This is in-

dicated on the D8 bit of the status register . PLL1 level is low when locked.

2. HORIZONTAL PART

2.1 Internal Input Conditions

A digital signal (horizontal sync pulse) is sent by

the sync processor to the horizontal input. It must

be positive (see Figure 4).

Synchronization occurs on the leading edge of the

internal sync signal.

The minimum value of Z is 0.7

µs.

Vertical synchro extraction is not allowed.

Figure 4.

2.2 PLL1

The PLL1 consists of a phase comparator, an ex-

ternal filter and a voltage-controlled oscillator

(VCO). The phase comparator is a ”phase fre-

quency” type designed in CMOS technology. This

kind of phase detector avoids locking on wrong

frequencies. It is followed by a ”charge pump”,

composed of two current sources: sunk and

sourced (typically I =1 mA when locked and

I = 140

µA when unlocked). This difference be-

tween lock/unlock allows smooth catching of the

horizontal frequency by PLL1. This effect is rein-

forced by an internal original slow down system

when PLL1 is locked, preventing the horizontal fre-

quency from changing too quickly. The dynamic

behaviour of PLL1 is fixed by an external filter

which integrates the current of the charge pump. A

”CRC” filter is generally used (see Figure 5).

Figure 5.

Figure 6. Block Diagram

Z

T

PLL1F

40

1.8k

Ω

10nF

4.7

µF

Lock/Unlock

Status

PHASE

ADJUST

Low

High

LOCKDET

COMP1

CHARGE

PUMP

PLL1F

R0

C0

40

42

41

VCO

OSC

HPOS

Adj.

44

H/HVIN

39 Filter

43

FC1

6