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OPERATING DESCRIPTION (continued)

Figure 7. Details of VCO

The VCO uses an external RC network. It delivers

a linear sawtooth resulting from the capacitor

charge and discharge . The current is proportional

to the one in the resistor. Typical thresholds for the

sawtooth are 1.6 V and 6.4 V.

The VCO control voltage varies between 3.0 V

and 3.8 V (see Figure 7). This VCO frequency

range is very small. The small effective frequency

is due to clamp intervention on the lowest filter val-

ue. The PLL1F filter voltage is set by a 4-bit DAC

with a voltage range of 3.0 to 3.8 V.

The sync frequency must always be higher than

the free running frequency. For example, when us-

ing a 60 kHz synchro range, the suggested free

running frequency is 56 kHz.

PLL1 ensures the coincidence between the lead-

ing edge of the sync signal and a phase reference

resulting from the comparison of:

– the VCO sawtooth

– an internal DC voltage I2C adjustable within the

range of 2.9V to 4.2V (corresponding to

±10%)

(see Figure 8).

A Lock/Unlock identification block, also included,

detects in real time whether PLL1 is locked on the

incoming horizontal sync signal or not.

The lock/unlock information is available through

The FC1 Pin (Pin 43) is used for decoupling the in-

ternal 6.4 V reference by a capacitor.

Figure 8. PLL1 Timing Diagram

RS

FLIP FLOP

0

C0

41

1.6V

6.4V

2

PLL1F

(Loop Filter)

40

42

R0

1.6V

6.4V

Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.9 V and 4.2 V.

Sawtooth

7/8 TH

1/8 TH

6.4V

3.4V (Reference for H Position)

Vb

(2.8V<Vb<4.2V)

1.6V

Phase REF1

HSynchro

The PLL1 ensures the exact coincidence between the signal phase REF and HSYNC.

A

±10% T

6