STV2000 datasheet(23/38 Pages) STMICROELECTRONICS

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STV2000

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OPERATING DESCRIPTION (continued)

3.2 I2C Control Adjustments

S correction shapes can then be added to this

ramp. This frequency-independent S correction is

generated internally. Its amplitudes is adjustable

via the I2C. S correction can be inhibited by apply-

ing the selected bits.

Finally, the amplitude of the S corrected ramp is

adjustable via the vertical ramp amplitude control

(VOUT) to drive an external power stage.

The gain of this stage can be adjusted (

± 25%) de-

pending on its register value.

The mean value of this ramp is driven by its own

2C register (vertical position) with :

VPOS = 7/16 x VREF-V = ± 300 mV.

Usually VOUT is sent through a resistive divider to

the inverting input of the booster. Since VPOS de-

rives from VREF-V, the bias voltage sent to the non-

inverting input of the booster should also derive

from VREF-V to optimize the accuracy

(see Figure 13).

Figure 13. AGC Loop Block Diagram

3.3 Basic Equations

As a first approximation, the amplitude of the ramp

on Pin 6 (VOUT) is calculated as follows:

VOUT - VPOS = (VOSC -VDCMID) x (1 + 0.25 (VAMP))

where :

VDCMID = 7/16 x VREF (middle value of the ramp on

Pin 5, typically 3.6V)

VOSC =V5 (ramp with fixed amplitude)

VAMP = -1 as minimum vertical amplitude register

value and +1 as maximum value.

VPOS is calculated according to:

VPOS = VDCMID + (0.4x VP )

where VP = -1 and +1 as respectively minimum

and maximum vertical position register value.

The current available on Pin 5 is:

IOSC =x VREF xCOSC xf

where

COSC = capacitor connected on Pin 5

f = synchronization frequency.

VSYNCIN

SYNCHRO

OSCILLATOR

DISCH.

OSC

CAP

CHARGECURRENT

TRANSCONDUCTANCE

AMPLIFIER

SAMPLING

CAPACITANCE

SCORRECTION

BREATH

6VOUT

VPOSITION

SUB09/7bits

VERT AMP

SUB08/7bits

VS AMP

SUB07/7bits

SAMPLING

Vlow

Sawth

Disch

REF

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