HD6417618A datasheet(366/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 334 of 610

REJ09B0131-0600

14.3.6

Serial Control Register (SCSCR)

SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt

requests, and selects the transmit/receive clock source. The CPU can always read and write to

SCSCR. SCSCR is initialized to H'0000 by a power-on reset.

Bit

Bit Name

Initial

value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TIE

R/W

Transmit Interrupt Enable

Enables or disables the transmit-FIFO-data-empty

interrupt (TXI).

Serial transmit data in the transmit FIFO data register

(SCFTDR) is send to the transmit shift register

(SCTSR). Then, the TDFE flag in the serial status

SCFTDR becomes less than the number of

transmission triggers. At this time, a TXI is requested.

0: Transmit-FIFO-data-empty interrupt request (TXI) is

disabled*

1: Transmit-FIFO-data-empty interrupt request (TXI) is

enabled

Note: * The TXI interrupt request can be cleared by

writing a greater number of transmit data than

the specified transmission trigger number to

SCFTDR and by clearing the TDFE bit to 0

after reading 1 from the TDFE bit, or can be

cleared by clearing this bit to 0.

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