HD6417618A datasheet(370/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 338 of 610

REJ09B0131-0600

14.3.7

Serial Status Register (SCFSR)

SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR

data, and the lower 8 bits indicate the status flag indicating SCIF operating state.

The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,

TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read

(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. SCFSR is

initialized to H'0060 by a power-on reset.

Bit

Bit Name

Initial

value

R/W

Description

PER3

PER2

PER1

PER0

Number of Parity Errors

Indicate the number of data including a parity error in

the receive data stored in the receive FIFO data

12 represents the number of parity errors in

SCFRDR. When parity errors have occurred in all 16-

byte receive data in SCFRDR, PER3 to PER0 show

FER3

FER2

FER1

FER0

Number of Framing Errors

Indicate the number of data including a framing error

in the receive data stored in SCFRDR. The value

indicated by bits 11 to 8 represents the number of

framing errors in SCFRDR. When framing errors have

occurred in all 16-byte receive data in SCFRDR,

FER3 to FER0 show 0.

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