HD6417618A datasheet(390/646 Pages) RENESAS

390 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 358 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

CTSIO

R/W

CTS Port Input/Output Control

Controls the

CTS pin in combination with the CTSDT bit

in this register and the MCE bit in SCFCR.

This bit is reserved in SCPTR_2 of SCIF channel 2

since SCIF channel 2 does not support the flow control.

CTSDT

*

R/W

CTS Port Data

Controls the

CTS pin in combination with the CTSIO bit

in this register and the MCE bit in SCFCR. Select the

CTS pin function in the PFC (pin function controller)

beforehand.

MCE

CTSIO

CTSDT:

CTS pin state

×:

Input (initial state)

Low level output

High level output

×:

Input to modem control logic

×: Don't care

The

CTS pin state is read from this bit instead of the set

value. This bit is reserved in SCPTR_2 of SCIF channel

2 since SCIF channel 2 does not support the flow

control.

SCKIO

R/W

SCK Port Input/Output Control

Controls the SCK pin in combination with the SCKDT

bit in this register, the C/A bit in SCSMR, and bits CKE1

and CKE0 in SCSCR.

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