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HD6417618A 数据表(PDF) 392 Page - Renesas Technology Corp |
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HD6417618A 数据表(HTML) 392 Page - Renesas Technology Corp |
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392 / 646 page  Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 6.00 Jun. 12, 2007 Page 360 of 610 REJ09B0131-0600 Bit Bit Name Initial value R/W Description 0 SPBDT * R/W Serial Port Break Data Controls the TxD pin in combination with the SPBIO bit in this register and the TE bit in SCSCR. The RxD pin state can also be monitored. Select the TxD or RxD pin function in the PFC (pin function controller) beforehand. TE SPBIO SPBDT: TxD pin state 0 0 ×: Input (initial state) 0 1 0: Low level output 0 1 1: High level output 0 × ×: Transmit data output according to serial core logic ×: Don't care The RxD pin state is read from this bit instead of the set value. Note: * This bit is read as an undefined value and the setting value is 0. |
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