HD6417618A datasheet(536/646 Pages) RENESAS

部件名	HD6417618A

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 19 User Debugging Interface (H-UDI)

Rev. 6.00 Jun. 12, 2007 Page 504 of 610

REJ09B0131-0600

19.4

Operation

19.4.1

TAP Controller

Figure 19.2 shows the internal states of the TAP controller. State transitions basically conform to

the JTAG standard.

Test-logic-reset

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-DR-scan

Run-test/idle

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Select-IR-scan

Figure 19.2 TAP Controller State Transitions

Note:

The transition condition is the TMS value at the rising edge of the TCK signal. The TDI

value is sampled at the rising edge of the TCK signal and is shifted at the falling edge of

the TCK signal. For details on change timing of the TDO value, see section 19.4.3, TDO

Output Timing. The TDO pin is high impedance, except in the shift-DR and shift-IR

states. A transition to the Test-Logic-Reset state is made asynchronously with TCK by

driving the

TRST signal 0.

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